2.
Pin configurations
Pin name
A0 - A17
Function
Addresses
44-lead PLCC
Top view
40-lead PDIP
Top view
O0 - O15
CE
Outputs
Chip enable
VPP
CE
1
2
40
39
VCC
A17
O12
7
39
A13
O15
3
38
A16
OE
NC
Note:
Output enable
No connect
Both GND pins must be
connected
O11
O10
O9
O8
GND
NC
O7
O6
O5
O4
8
9
10
11
12
13
14
15
16
17
38
37
36
35
34
33
32
31
30
29
A12
A11
A10
A9
GND
NC
A8
A7
A6
A5
O14
O13
O12
O11
O10
O9
O8
GND
O7
O6
4
5
6
7
8
9
10
11
12
13
37
36
35
34
33
32
31
30
29
28
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
3.
System considerations
O5
O4
O3
O2
O1
O0
OE
14
15
16
17
18
19
20
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
Switching between active and standby conditions via the chip enable pin may produce transient voltage excursions. Unless
accommodated by the system design, these transients may exceed datasheet limits, resulting in device nonconformance.
At a minimum, a 0.1μF, high-frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This
capacitor should be connected between the V CC and ground terminals of the device, as close to the device as possible.
Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7μF bulk electrolytic
capacitor should be utilized, again connected between the V CC and ground terminals. This capacitor should be positioned as
close as possible to the point where the power supply is connected to the array.
Figure 3-1.
Block diagram
2
Atmel AT27C4096
0311J–EPROM–4/11
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